VLSI - Verification
VHDL / Verilog RTL/Testbench coding
Development of Verification Environment (VE) / Verification Component (VC) using Specman ‘e’
Writing tests, functional coverage using ‘e’ and mapping these to Verification planRequired Skills
Exposure to scripting language/s
Experience of VHDL and/or Verilog programming languages.
An excellent knowledge of digital design / verification techniques
Minimum 2yrs experience with Specman based verification for developing VE, VC, writing tests, functional coverage.Desirable Skills
Expertise on USB2.0, SATA, HDMI protocols, IPs and UVCs.
Expertise with C++ and systemC programming / modeling.
Knowledge / experience with TLM, OVM / UVM, multi-language verification environment.
Experience with code coverage tools
Knowledge / experience with System VerilogExperience : 2-3 yrs
Qualifications : B.Tech / B.E. with first class in electronic engineering or related stream.
Thanks & Regards,
Sana
Roland & Associates - Leaders in Social Media Recruitment
Reach Us : 080 42821616
Email: sana@roljobs.com
Website: www.roljobs.net // www.roljobs.com // http://sana-roljobs.blogspot.com/
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