VLSI - Verification Engineer for Pune - Sana@roljobs.com

VLSI - Verification Engineer for Pune

The Role
Primary responsibilities will include
    Development of Verification Environment (VE) / Verification Component (VC) using Specman ‘e’
    Writing tests, functional coverage using ‘e’ and mapping these to Verification plan
    Functional verification of the design and achieve verification goals
    VHDL / Verilog RTL/Testbench coding

Required Skills
    An excellent knowledge of digital design / verification techniques
    Minimum 2yrs experience with Specman based verification for developing VE, VC, writing tests, functional coverage.
    Experience of VHDL and/or Verilog programming languages.
    Exposure to scripting language/s

Desirable Skills
    Expertise on USB2.0, SATA, HDMI protocols, IPs and UVCs.
    Expertise with C++ and systemC programming / modeling.
    Knowledge / experience with TLM, OVM / UVM, multi-language verification environment.
    Experience with code coverage tools
    Knowledge / experience with System Verilog

Experience :  2-3 yrs in the above mentioned areas.
Qualifications :   Minimum B.Tech / B.E. with first class in electronic engineering or related stream.



Thanks & Regards,
Sana
Roland & Associates - Leaders in Social Media Recruitment.
Tel: 91-80-4282-1616 , 
E-Mail: sana@roljobs.com
Internet: www.roljobs.com ; www.roljobs.net ;